Research Interests

  • Compiler optimizations
  • Parallel architectures, including thread-level, data-level and instruction-level parallelism
  • Compiler middle-end and back-end analysis and transformations targeting architectures to exploit such parallelism

Short bio

  • Principle Engineer at Intel Israel (Haifa), working on LLVM-based compiler optimizations for Intel platforms. Joined on Dec. 2011
  • Co-supervising PhD and MSc students; referee of theses
  • Organizing conferences, including CATC and PACT 2016
  • Spent a short sabbatical at Princeton University during the summer of 2011
  • Worked at IBM Haifa Research Lab on compiler optimizations, 1997-2011
    • spent the last seven years building and managing the compiler technologies group
    • research: including publications in conferences (e.g., PLDI, PACT)
    • development: including GCC (e.g., modulo-scheduling, auto-vectorization by group members)
    • spent one year on international assignment at IBM T.J.Watson Research Center in Yorktown Heights, NY 
  • A member of ACM. A member of the European HiPEAC Network of Excellence from 2005, hosted eight HiPEAC summer PhD internships
  • Engaged in teaching Compiler courses starting in 2004
  • Studied Math at Tel-Aviv University, Ph.D. on Coloring Problems in Combinatorics in 2002.
  • Worked as a SW developer at IET Intelligent Electronics (renamed ClickSoftware Technologies), 1992-1997.

Picture (at HiPEAC’12, taken by Nacho Navarro 1958 – 2016)

Recording of the talk on “Vectorizing Loops with VPlan – Current State and Next Steps” given at the LLVM US Dev Meeting on Oct. 18, 2017

Recording of the invited talk on “Compiling for Scalable Computing Systems – the Merit of SIMD” given at TCE Conference on June 2, 2015